As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. Yet as feature size continues to become smaller and smaller, development of improved materials for cell dielectrics as well as the cell structure are important. The feature size of 256 Mb DRAMs will be on the order of 0.25 micron, and conventional dielectrics such as SiO.sub.2 and Si.sub.3 N.sub.4 might not be suitable because of small dielectric constants.
Highly integrated memory devices, such as 256 Mbit DRAMs, are expected to require a very thin dielectric film for the 3-dimensional capacitor of cylindrically stacked or trench structures. To meet this requirement, the capacitor dielectric film thickness will be below 2.5 nm of SiO.sub.2 equivalent thickness. Chemical vapor deposited (CVD) Ta.sub.2 O.sub.5 films are considered to be very promising cell dielectric layers for this purpose, as the dielectric constant of Ta.sub.2 O.sub.5 is approximately three times that of conventional Si.sub.3 N.sub.4 capacitor dielectric layers. However, one drawback associated with Ta.sub.2 O.sub.5 dielectric layers is undesired leakage current characteristics. Accordingly, although Ta.sub.2 O.sub.5 material has inherently higher dielectric properties, as-deposited Ta.sub.2 O.sub.5 typically produces unacceptable results due to leakage current.
Densification of Ta.sub.2 O.sub.5 as deposited has been reported to significantly improve the leakage characteristics of such layers to acceptable levels. Prior art densification of such layers includes exposing the Ta.sub.2 O.sub.5 layer to extreme oxidizing conditions. Undesirably, however, such has a tendency to form an SiO.sub.2 layer intermediate/between the polysilicon and Ta.sub.2 O.sub.5. Further and regardless, a thin SiO.sub.2 layer will also typically inherently form during the Ta.sub.2 O.sub.5 deposition due to the presence of oxygen at the polysilicon layer interface. It would be desirable to remove or eliminate this SiO.sub.2 layer intermediate the Ta.sub.2 O.sub.5 and polysilicon layers, yet allow for such desired densification.
One prior art technique reported includes exposing the polysilicon layer to rapid thermal nitridation prior to subsequent deposition of the Ta.sub.2 O.sub.5 layer. Such are reported by Kamiyama et al., "Ultrathin Tantalum Oxide Capacitor Dielectric Layers Fabricated Using Rapid Thermal Nitridation prior to Low Pressure Chemical Vapor Deposition", J. Electrochem. Soc., Vol. 140, No. 6, June 1993 and Kamiyama et al., "Highly Reliable 2.5 nm Ta.sub.2 O.sub.5 Capacitor Process Technology for 256 Mbit DRAMs", 830-IEDM 91, pp. 32.2.1-32.2.4. Such rapid thermal nitridation includes exposing the subject polysilicon layer to temperatures of from 800.degree. C. to 1100.degree. C. for sixty seconds in an ammonia atmosphere at atmospheric pressure. The nitride layer acts as a barrier layer to oxidation during Ta.sub.2 O.sub.5 deposition and subsequent high temperature densification processes to prevent oxidation of the underlying polysilicon electrode. These processes do however have several drawbacks, including the undesired high temperature cycling and formation of a fairly thick native SiO.sub.2 on the nitride in series with the Ta.sub.2 O.sub.5, all of which adversely effects the realization of high capacitance promised by inherent Ta.sub.2 O.sub.5 layers.
It would be desirable to improve upon such prior art processes enabling utilization of Ta.sub.2 O.sub.5 layers in capacitor constructions.